New Products (From: Xilinx NEWS Date:24/06/2012 )

2012-8-30

From: Xilinx NEWS     Date: 24/06/2012 

Xilinx expands FEC IP core Offering for 2.5G, 10G, 40G and 100G applications 

Xilinx, Inc has expanded Forward Error Correction (FEC) Intellectual Property (IP) Core offering, the offering includes GFEC eFEC and high gain FEC (xFEC) solutions used to obtain error control in signal transmission and extend the distance of a transmission that reduces the number of regenerators (hops) along the route, which reduces OpEx and CapEx costs for network operators. 

The FEC cores - which include GFEC IP cores for 2.5G, 10G, 40G and 100G applications , legacy 10G eFECs and a Xilinx Extended FEC (xFEC) IP core for 100G applications - were designed internally and optimized specifically for Xilinx FPGAs to occupy less silicon real estate than non-Xilinx IP cores, making them the smallest FEC cores available. Xilinx is also working to add 400G GFEC for leading edge applications to be available Q2 2013. 

"As bandwidth demands increase and the tolerance for errors and latency decreases, system designers are looking for new ways to expand available bandwidth and improve the quality of transmission," said Nick Possley, Xilinx senior director wired communications. "To solve these challenges, Xilinx has extended our leadership position in the OTN marketplace by delivering this expanded offering of FEC IP cores for 2.5G, 10G, 40G ,100G and 400G applications. The power/performance available in our 7 series FPGA family combined with this FEC portfolio enables our customers to achieve higher data rates, increase bandwidth and reduce system costs within the OTN application space." 

The Xilinx OTU1, 2, 3 and 4 (2.5G, 10G, 40G and 100G) GFEC IP cores are compliant to the ITU G.709 standard and is available now. The 100G high gain xFEC will be available in December 2012.